EDA

• 2024/11/16 Using glbl.v module in a Verilog simulation in Vivado
• 2024/10/26 Parse your value change dumps
• 2024/10/05 From zero to RISC-V in hardware, in 6 minutes
• 2024/09/03 bazel rules for GHDL
• 2024/07/08 Remote programming of an AMD (fka Xilinx) Artix-7 device
• 2023/11/20 Packaging AMD Xilinx Vivado ML Standard edition in a Docker container