Hermetic EDA and Bazel Builds
Move synthesis, place-and-route, simulation, and firmware into one hermetic Bazel build graph with remote caching and pinned toolchains.
HDL Factory helps engineering teams build FPGA, RISC-V, and board designs with the same reproducibility and test automation as software. We put vendor EDA tools, simulators, firmware, and PCB flows into one hermetic Bazel build graph.
Move synthesis, place-and-route, simulation, and firmware into one hermetic Bazel build graph with remote caching and pinned toolchains.
Board bring-up, custom IP cores, RISC-V SoC integration, and cycle-exact FPGA simulation for Linux and Fuchsia targets.
Automated testbenches, waveform pipelines, and continuous integration that run on every pull request.
Schematics in Python, routed PCBs checked by DRC and netlist parity tests, parametric enclosures, and byte-reproducible factory packages.
Our books and open-source Bazel rulesets document the methods we use in client engagements.
rules_vunit packages VUnit, the unit-testing framework for VHDL, as a hermetic Bazel module. Testbenches written against VUnit check, run, and logging libraries execute as standard bazel test targets. In cocoapuffs-fpga, …
“You deserve nice circuit diagrams!” Every digital design document needs pictures. A clean block diagram communicates dataflow, bus widths, and control hierarchy in seconds. Reading through hundreds of lines of RTL or …
Linux 6.18 now boots on FireSim’s Rocket design on an Alinx AX7A200B board. The host reaches the board over an Ethernet cable, as in the last post. The whole run takes 4 min 36 s: 4 min 22 s to load the software, and 13 …
filmil’s Auto Reload is a Chrome extension that reloads a tab every few seconds, minutes or hours, and can do nothing else. It asks for two permissions, shows no warning when you install it, and cannot read the pages it …
UberDDR4 is an open-source DDR4 SDRAM controller and PHY for FPGAs, written by Angelo C. Jacobo. It connects a Wishbone master to DDR4 memory. It handles initialization, command timing, bank scheduling, refresh and PHY …