Vivado

• 2026-08-17 Bazel all the way down: how I build programmable hardware #bazel#FPGA#HER

  This is a description of how I build programmable hardware. Everything that goes into Cocoapuffs, my RISC-V system-on-chip on an Artix-7 FPGA: the RTL, the firmware, the simulations, the synthesis, the bitstream, and the …

• 2026-08-10 rules_vivado: FPGA Synthesis and Place-and-Route in Bazel #bazel#FPGA#Vivado

  rules_vivado drives the AMD/Xilinx Vivado FPGA toolchain from Bazel: VHDL and Verilog compile, elaborate, simulate, synthesize, place-and-route, generate a bitstream, and program the device, all as hermetic Bazel build …

• 2026-07-19 Booting Fuchsia’s Zircon on a homebrew RISC-V o n Artix-7 FPGA #FPGA#RISC-V#Zircon

  Fuchsia’s Zircon kernel now boots on Cocoapuffs, my homebrew RISC-V system-on-chip an AMD Artix-7 FPGA: as far as I know, the first Fuchsia boot on programmable hardware. The boot video and the full chain, from a SERV …

• 2026-04-11 mkill: a memory watchcat #bazel#go#GCP

  mkill is a Go program that continuously monitors memory usage of the programs owned by the current user. It kills the program with the sharpest rise in memory utilization when the overall system memory occupancy goes …

• 2026-02-01 Inventory of programmable hardware tooling #bazel#FPGA#Vivado

  A link page of interesting libraries and utilities I found. Libraries, utilities, etc. https://registry.bazel.build/modules/rules_verilator https://github.com/lromor/fpga-assembler …

• 2025-09-01 Writing XDC Clock Constraints for Vivado #FPGA#Vivado

  Writing XDC Clock Constraints for Vivado This guide explains how to properly constrain a digital design with multiple clocks in an XDC (Xilinx Design Constraints) file, specifically for use in Vivado batch mode. We’ll …

• 2025-06-19 Packaging AMD Xilinx Vivado ML Standard edition 2025.1 in a Docker container #Xilinx#FPGA#Docker

  I updated the repository https://github.com/filmil/vivado-docker/ with the changes required to package Vivado 2025.1. As of this writing, version 2025.1 is the last published version. I hope that the updated version will …

• 2024-11-16 Using glbl.v module in a Verilog simulation in Vivado #FPGA#Vivado#Xilinx

  A quick note about correct use of glbl.v in a Verilog simulation in Vivado. This note is way less confusing than any notes you may find elsewhere on the Internet. glbl.v is a small collection of “global” signals that are …

• 2024-10-05 From zero to RISC-V in hardware, in 6 minutes #FPGA#Bazel#Xilinx

  From zero to RISC-V in hardware, in 6 minutes Program your FPGA with a one-liner command. It’s a kind of magic. This is a project in sustainable FPGA development that I have been working on. It ties together several …

• 2024-07-08 Remote programming of an AMD (fka Xilinx) Artix-7 device #FPGA#Vivado#Xilinx

  Summary Here is how you can set up a hardware server (hw_server) in AMD Vivado 2023.2. Once you do this, that you can move your workbench to a virtual machine in your cloud of choice - mine is GCP - but program a device …

• 2023-11-20 Packaging AMD Xilinx Vivado ML Standard edition in a Docker container #Xilinx#FPGA#Docker

  A while back I wanted to make a hermetic environment for repeatably running Docker tooling. The results are here: https://github.com/filmil/vivado-docker/ At this time, it’s only able to run the GUI version of the tool. …