VHDL

• 2026-07-23 The FPGA Hardware Interview: A Topic Guide with Questions and Exercises #FPGA#interviews#VHDL

  Interviews for FPGA and digital-design roles draw from a stable, well-defined body of knowledge, yet candidates routinely stumble on it because the questions are asked crisply and must be answered under pressure. I am …

• 2025-07-14 Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design #EDA#VHDL#FPGA

  I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result. Mastering Resolved Signals in VHDL: A Comprehensive Guide for Digital Design 1. Introduction to Signals in VHDL The …

• 2025-07-07 How to shoot yourself in the foot with inout signals #EDA#VHDL#FPGA

  How to shoot yourself in the foot with inout signals They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity …

• 2025-06-29 VHDL IEEE Libraries and Numeric Type Conversion: A Definitive Reference #EDA#VHDL#FPGA

  I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while. VHDL IEEE Libraries and Numeric Type Conversions: A Definitive …

• 2024-10-26 go-vcd-parser: a tested VCD parser and toolkit in Go #EDA#Verilog#VHDL

  go-vcd-parser reads Value Change Dump (VCD) files, the waveform format that simulators such as Verilator, Icarus Verilog and nvc write. The format is defined in IEEE 1800. The parser handles the 4-value format and the …

• 2024-09-03 bazel rules for GHDL #bazel#VHDL#EDA

  bazel rules for GHDL I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog. This for example allows running VHDL code in a Verilator simulation. Commercial …