I asked Gemini to teach me about the VHDL resolved signals. What you read below is the result.
They say that no good deed goes unpunished. Here’s an example of a footgun in VHDL which stems from in my view an eminently reasonable desire to keep the entity interface definitions compact.
I asked Gemini to teach me the VHDL type conversions. What you read below is the result. An annoying generated podcast will be available for a while.
bazel rules for GHDL
I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog.