bazel rules for GHDL

2024/09/03

bazel rules for GHDL

I present to you https://github.com/filmil/bazel_rules_ghdl: a set of bazel rules for converting VHDL into Verilog.

This for example allows running VHDL code in a Verilator simulation. Commercial tools usually do not care what HDL the modules are written in. But usually commercial tools are the final mile in open source HDL development.

Before you get there, you want the ability to run reasonably detailed simulations.

What?

This repository contains a bazel rule set for running ghdl, the VHDL simulator and synthesizer, specifically to convert VHDL designs into Verilog.

This is useful as Verilog open source tools are way more popular than VHDL ones, and often useful modules may be written in both languages. By converting to Verilog, you automatically get a chance to use the open source HDL ecosystem of tools.

Why?

Because often VHDL is not supported by open source tooling, while Verilog is. These rules use ghdl’s “synthesis into Verilog” mode to do the conversions. It seems that ghdl is able to convert large designs, as exemplified here.

How?

While working on bazel support for EDA tools, I noticed a particular toolink bias towards Verilog (not even SystemVerilog) in open source tooling. This is an issue if your designs are mainly built in VHDL. The set of bazel rules for GHDL at https://github.com/filmil/bazel_rules_ghdl fixes that to an acceptable extent, by converting your VHDL code into Verilog. The output of the conversion process can then be used in other tooling that expects Verilog as input.

Example use

The following shows the contents of a BUILD.bazel file which builds a target //:verilog from a VHDL library.

load("@bazel_rules_ghdl//:rules.bzl", "ghdl_library", "ghdl_verilog")

ghdl_library(
  name = "lib",
  srcs = [ "hello.vhdl", ]
)

ghdl_verilog(
  name = "verilog",
  lib = ":lib",
  unit = "my_module",
)

Prerequisites

Everything else will be downloaded for use the first time you run the build.

Examples

In general, see integration/ for example use.

ghdl_verilog

Use GDHL to convert a vhdl file to verilog. The build process will build an intermediate result of a single VHDL library as well.

cd integration && bazel build //… && cat bazel-bin/verilog.v

ghdl_library

If you want to see how it builds a library, run this:

cd integration && bazel build //:lib

Notes

References